Zeitschrift für Kernenergiewissenschaft und Energieerzeugungstechnologie

Ein effizienter Entwurf eines FSM-basierten 32-Bit-Pipeline-Multiplikators ohne Vorzeichen unter Verwendung von Verilog HDL

Hema Chitra * , R. Dhanasekaran, V. Rajya Ganesh und Preeti Maddhyeshia

This paper shows a modification to FSM based 32-bit pipelined multiplier. It uses Carry Look Ahead Adders (CLA’s) and Carry Select Adders (CSA) in place of Ripple Carry Adders (RCA’s) in 32-bi               t FSM based pipelined multiplier for reducing the carry propagation delay. The proposed hardware design is based on shift and add algorithm for multiplication process. Our suggested pipelined multiplier design has reduced adder and added the partial product sequentially to increase maximum operating frequency and reduce hardware resources. Synthesis report shows that modified FSM based 32-bit pipelined multiplier has less delay, less usage of logical resources, than FSM based pipelined multiplier. Simulation was done in Xilinx Vivado 2017.4(Verilog HDL).

The proposed design instantiates carry select adder for the partial product addition process, carry select adder is faster than ripple carry adder. The tradeoff between delay and power, Delay has been reduced and power increased when compared to the existing method. The proposed method can be used for the high-speed pipelined multiplication operation.